CCE Faculty Proceedings, Presentations, Speeches and Lectures
Target Environment Simulation and its Impact on ArchitectureValidation
Presentation Date
12-13-2014
Document Type
Conference Proceeding
Proceedings Title
MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification
ISSN
1550-4093
Description
Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.
DOI
10.1109/MTV.2013.27
First Page
74
Last Page
76
NSUWorks Citation
Mason, Jack L. and Simco, Gregory, "Target Environment Simulation and its Impact on ArchitectureValidation" (2014). CCE Faculty Proceedings, Presentations, Speeches and Lectures. 40.
https://nsuworks.nova.edu/gscis_facpres/40
Comments
Conference held in Austin, TX, December 11-13, 2013