CCE Theses and Dissertations

Date of Award


Document Type


Degree Name

Doctor of Philosophy (PhD)


College of Computing and Engineering


Sumitra Mukherjee

Committee Member

Michael J. Laszlo

Committee Member

Francisco J. Mitropoulos


Hardware Design Verification, commonly called verification, is the process of functionally verifying a design that was written in a Register Transfer Language (RTL) based on the specification. The most common methodology in practice today uses the Universal Verification Methodology (UVM). In addition to being a methodology, UVM is also a collection of object-oriented base classes written in SystemVerilog. A UVM testbench is created that serves as a harness for the Design Under Test (DUT). Stimulus, with constrained random inputs, is written that exercises the design. Constrained Random Verification (CRV) is used to find functional errors in the design and to meet coverage goals.

One form of coverage is functional coverage. Functional coverage is defined and developed by the verification engineer to verify that certain scenarios are covered during simulation. Coverage is created as a collection of coverpoints, and each coverpoint has one or more bins to indicate what is or is not hit. As a simple example, one coverpoint could be the write indicator for a First-In First-Out (FIFO) queue. This coverpoint would have two bins: one if the write indicator was high and another if it were low. For a large System-on-Chip (SOC) design, the number of bins to be covered could number in the tens of thousands. Reaching 100\% coverage on such a design would require a large amount of compute space and potentially thousands of simulations running daily. The time it takes to analyze the coverage results and develop new stimulus to cover missing cases can take weeks to months, depending on the complexity of the design. To improve the efficiency and time it takes to reach coverage closure, this dissertation study evaluates the use of machine learning techniques. More specifically, this study uses a combination of Supervised Learning, Reinforcement Learning, and Bayesian Optimization to select constraints to reach coverage closure more efficiently.

Using two different RTL models, the results of this study show that using Machine Learning models reduces time to coverage closure. Using a combination of Bayesian Optimization with Reinforcement Learning, constraints were optimized so that the number of simulations required to reach 100% coverage was much less than using constrained random constraints. This research highlights the effectiveness of using Machine Learning in the Hardware Design Verification flow.