CEC Faculty Proceedings, Presentations, Speeches and Lectures

Title

Target Environment Simulation and its Impact on ArchitectureValidation

Document Type

Conference Proceeding

Presentation Date

12-13-2014

Conference Name / Publication Title

MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification

ISSN or ISBN

1550-4093

First Page

74

Last Page

76

Description

Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.

Comments

Conference held in Austin, TX, December 11-13, 2013

DOI

10.1109/MTV.2013.27

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