Target Environment Simulation and its Impact on ArchitectureValidation
Conference Name / Publication Title
MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification
ISSN or ISBN
Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.
Mason, Jack L. and Simco, Gregory, "Target Environment Simulation and its Impact on ArchitectureValidation" (2014). CEC Faculty Proceedings, Presentations, Speeches and Lectures. 40.